Design a Flexible Software Development Environment on NetFPGA Platform

Abstract:

Among numerous embedded platforms, NetFPGA provides developers with a freely programmable FPGA component to design custom functionalities in networking. However, most hardware projects are developed based on reference designs without embedded operating system. For hybrid developments on multi-layers, there will be some difficulties to apply. On the other hand, due to the limited resources on embedded platform, both performance and flexibility need to be concerned on implementation. And for networking processing, it is quite difficult to adjust control parameters without software environment. Therefore, this paper proposes an integrated architecture using PowerPC processor on NetFPGA and embedded Linux operating system on NetFPGA platform. This not only provides developers with an environment for software execution which added more flexibility, but also enhanced the system to provide more applied possibilities on development.

• Periodical: Applied Mechanics and Materials (Volumes 411-414)
• Pages: 1665-1669
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.411-414.1665
• Online since: September 2013
• Authors: Pang Wei Tsai, Hou Yi Chou, Mon Yen Luo, Chu Sing Yang
• Keywords: Embedded System, NetFPGA, POWERPC

References

[1] NetFPGA - An Open Platform for Gigabit-rate Network Switching and Routing; John W. Lockwood, Nick McKeown, Greg Watson, Glen Gibb, Paul Hartke, Jad Naous, Ramanan Raghuraman, and Jianying Luo; MSE 2007, San Diego, June (2007).

DOI: 10.1109/mse.2007.69

[2] NetFPGA: Reusable Router Architecture for Experimental Research; Jad Naous, Glen Gibb, Sara Bolouki, and Nick McKeown; SIGCOMM, Seattle, WA, August (2008).

DOI: 10.1145/1397718.1397720

[3] IBM PowerPC 405 Embedded Core, https: /www-01. ibm. com/chips/techlib/techlib. nsf/techdocs/852569B20050FF778525699300651D97/$file/PowerPC405_Nov2006. pdf.

[4] NetFPGA PCB Layout, http: /wiki. netfpga. org/NetFPGA_PCB_r3. pdf.

[5] XPS UART Lite, http: /www. xilinx. com/support/documentation/ip_documentation/xps_uartlite. pdf.

[6] Xilinx ISE Design Suite, http: /www. xilinx. com/products/design-tools/ise-design-suite.

[7] IBM CoreConnect Bus Architecture, https: /www-01. ibm. com/chips/techlib/techlib. nsf/techdocs/3BBB27E5BCC165BA87256A2B0064FFB4/$file/PlbBus_as_01_pub. pdf.

[8] Xilinx Platform Studio and the Embedded Development Kit, http: /www. xilinx. com/tools/platform. htm.

[9] Xilinx Memory Interface Generator, http: /www. xilinx. com/products/intellectual-property/MIG. htm.

[10] ISO/IEC 7498-1 Open Systems Interconnection Model, http: /www. iso. org/iso/catalogue_detail. htm?csnumber=20269.

[11] IEEE Standard 802. 3: CSMA/CD Access Method and Physical Layer Spec, http: /standards. ieee. org/getieee802/download/802. 3-2008_section2. pdf.

[12] RGMII v2. 0 spec, http: /www. hp. com/rnd/pdfs/RGMIIv2_0_final_hp. pdf.

[13] Broadcom BCM5464SR, http: /zh-tw. broadcom. com/products/Physical-Layer/Gigabit-Ethernet-PHYs/BCM5464SR.

[14] Xilinx XAPP, http: /www. xilinx. com/support/documentation/application_notes/xapp692. pdf.

[15] Buildroot, http: /buildroot. uclibc. org.

[16] BusyBox, http: /www. busybox. net.

[17] Lmbench, http: /www. bitmover. com/lmbench.