Effects of Data's Bit-Width on Digital Logic Design

Sheng Chang; Heng Cai; Hao Wang; Jin He; Qi Jun Huang

doi:10.4028/www.scientific.net/AMM.411-414.1670

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 411-414Effects of Data's Bit-Width on Digital Logic...

Effects of Data's Bit-Width on Digital Logic Design

Abstract:

Single precision can only achieve 6-7 decimal places, which does not satisfy accuracy demand in many calculations. Double precision can get 13-14 decimal places, but the resource cost is high. In this paper, effects of data bit-width on digital logic design are studied. The accuracy of different bit-width is determined. Then, addition operation, multiplication operation and matrix multiplication with different bit-width are tested on FPGA platform. The results show bit width and circuit design platform have obvious effect on resource cost and circuit efficiency. Finally, a bit-width based circuit design optimization method is proposed.

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Periodical:

Applied Mechanics and Materials (Volumes 411-414)

Pages:

1670-1673

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.411-414.1670

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Online since:

September 2013

Authors:

Sheng Chang, Heng Cai, Hao Wang, Jin He, Qi Jun Huang

Keywords:

Accuracy Analysis, Bit-Width, Field-Programmable Gate Array (FPGA), Resource Cost

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