IPs Design of FPGA for High-Resolution Image Process

Abstract:

With the progress of science and technology, the image resolution of monitoring systems is entered the Full-HD (High Definition) era. The Full-HD refers to resolution of 1920X1080 (1080p), and the image refresh frequency is 30fps (Frames Per Second). Therefore, this thesis uses FPGA as image system processor, as well as uses AFE to implement a camera module. First, the dual-channel serial signal from AFE is converted into single-channel parallel signal, and the image is processed following our image processing procedure before charting and export. The image processing procedure includes AEC, auto color balance, color filter array interpolation, color correction, noise filter, gamma correction and dynamic range correction. Our algorithm counts information instantly, and calculates better correcting function content, so that we can display the brighter and darker parts of images clearly in different environments. Compared with a part of CCD digital cameras on the market, our ISP has better performance in SNR. Finally, the AWB mean error of our ISP design is less than 0.02%, it is difficult to be perceived by human eyes.

• Periodical: Applied Mechanics and Materials (Volume 418)
• Pages: 257-260
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.418.257
• Online since: September 2013
• Authors: Wen Tzeng Hunag, Chao Nan Huang, Sun Yen Tan, Chiu Ching Tuan, Chin Hsing Chen, Xing Bao Wang
• Keywords: CCD, High-Resolution Camera, Image System Processor (ISP), SNR, White Balance

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