FPGA Implementation of a High-Speed Two Dimensional Discrete Wavelet Transform

Abstract:

This paper proposes high-speed VLSI architecture for implementing a forward two-dimensional discrete wavelet transform (2D DWT). The architecture is based on 2D DWT mathematical formulae. A pipelined scheme is used to increase the clock rate, which allows its critical path to take only one adder delay. The proposed design enables 100% hardware use and faster computing than other 2D DWT architecture. It is easily extended to multilevel decomposition because of its regular structure. It requires N/2 by N/2 clock cycles for k-level analysis of an N by N image. The proposed architecture was coded in VerilogHDL and verified on a real time platform which uses a CMOS image sensor, a field-programmable gate array (FPGA) and a TFT-LCD panel. In the simulation, the design worked with a clock period of 132.38MHz. It can be used as an independent IP core for various real-time applications.

• Periodical: Applied Mechanics and Materials (Volumes 479-480)
• Pages: 508-512
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.479-480.508
• Online since: December 2013
• Authors: Chin Fa Hsieh, Tsung Han Tsai
• Keywords: Discrete Wavelet Transform (DWT), VerilogHDL, VLSI

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