[1]
Robert J. Mceliece. The Theory of Information and Coding, 2nd ed. Cambridge University Press, (2003).
Google Scholar
[2]
Kolarik, V.; Mir, S.; Lubaszewski, M.; Courtois, B.; , Analog checkers with absolute and relative tolerances, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol. 14, no. 5, pp.607-612, May (1995).
DOI: 10.1109/43.384424
Google Scholar
[3]
Vasquez, D.; Rueda, A.; Huertas, J.L., A practical implementation of fault-tolerant switched-capacitor circuits, Circuits and Systems, 1991, IEEE International Sympoisum, vol., no., pp.1565-1568 vol. 3, 11-14 Jun (1991).
DOI: 10.1109/iscas.1991.176676
Google Scholar
[4]
Sarah J. Johnson. Iterative Error Correction: Turbo, Low-Density Parity-Check and Repeat-Accumulate Codes, Cambridge University Press, (2009).
DOI: 10.1017/cbo9780511809354.003
Google Scholar
[5]
Frederic P. Miller, Agnes F. Vandome, John McBrewster. Cyclic Redundancy Check: Computation of CRC, Mathematics of CRC, Error detection and correction, Alphascript Publishing, (2009).
Google Scholar
[6]
Matsubara, T.; Koga, Y., A proposal for error-tolerating codes, Fault-Tolerant Computing, 1993. FTCS-23. Digest of Papers., The Twenty-Third International Symposium on , vol., no., pp.130-136, 22-24 Jun (1993).
DOI: 10.1109/ftcs.1993.627315
Google Scholar