Combined Effects of Guard Rings and Buried n+ Layer on Mitigating Charge Collection and Charge Sharing in 90 nm CMOS Process

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A model of combining of guard rings and buried n+ layer in mitigating charge collection and charge sharing is presented in this paper. 3-D TCAD simulation results indicate that for 90-nm CMOS process, PMOS charge collection and charge sharing can be mitigated more effectively with the combination model than the solely use of guard rings or buried n+ layer. With the combination, a noticeable improvement on angled ion strikes is also represented. The model shows a significant advantage in high-energy ion strikes and angled ion strikes.

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303-308

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February 2014

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© 2014 Trans Tech Publications Ltd. All Rights Reserved

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[1] O. Musseau, F. Gardic, P. Roche, T. Corbiere, R. A. Reed, S. Buchner, P. McDonald, J. Melinger, L. Tran, and A. B. Campbell, Analysis of multiple bit upsets (MBU) in CMOS SRAM, [J], IEEE Trans. Nucl. Sci., 1996 43 (6) 2879-2888.

DOI: 10.1109/23.556881

Google Scholar

[2] O. A. Amusan, A. F. Witulski, L. W. Massengill, B. L. Bhuva, P. R. Fleming, M. L. Alles, A. L. Sternberg, J. D. Black, and R. D. Schrimpf, Charge collection and charge sharing in a 130 nm CMOS technology, [J], IEEE Trans. Nucl. Sci., 2006 53 (6) 3253-3258.

DOI: 10.1109/tns.2006.884788

Google Scholar

[3] B. D. Olson, O. A. Amusan, S. Dasgupta, L. W. Massengill, A. F. Witulski, B. L. Bhuva, M. L. Alles, K. M. Warren, and D. R. Ball, Analysis of parasitic PNP bipolar transistor mitigation using well contacts in 130 nm and 90 nm CMOS technology, [J], IEEE Trans. Nucl. Sci., 2007 54 (4) 894-897.

DOI: 10.1109/tns.2007.895243

Google Scholar

[4] O. A. Amusan, L. W. Massengill, M. P. Baze, B. L. Bhuva, A. F. Witulski, J. D. Black, A. Balasubramanian, M. C. Casey, D. A. Black, J. R. Ahlbin, R. A. Reed, and M. W. McCurdy, Mitigation techniques for single-event-induced charge sharing in a 90-nm bulk CMOS process, [J], IEEE Trans. Device Mater. Rel., 2009 9 (2) 311-317.

DOI: 10.1109/tdmr.2009.2019963

Google Scholar

[5] O. A. Amusan, M. C. Casey, B. L. Bhuva, D. McMorrow, M. J. Gadlage, J. S. Melinger, and L. W. Massengill, Laser verification of charge sharing in a 90 nm bulk CMOS process, [J], IEEE Trans. Nucl. Sci., 2009 56 (6) 3065-3070.

DOI: 10.1109/tns.2009.2032285

Google Scholar

[6] B. D. Olson, D. R. Bell, K. M. Warren, L. W. Massengill, N. Haddad, and R. Richards, Impact of scaling on SEU immunity for a fixed SRAM topology, presented at the Hardened Electronics Radiation Technology (HEART) 2005, Tampa, FL, Mar. (2005).

Google Scholar

[7] O. A. Amusan, L. W. Massengill, B. L. Bhuva, S. Dasgupta, A. F. Witulski, and J. R. Ahlbin, Design techniques to reduce SET pulse widths in Deep-Submicron combinational logic, [J], IEEE Trans. Nucl. Sci., 2007 54 (6) 2060-(2064).

DOI: 10.1109/tns.2007.907754

Google Scholar

[8] B. Narasimham, B. L. Bhuva, R. D. Schrimpf, L. W. Massengill, M. J. Gadlage, T. W. Holman, A. F. Witulski, W. H. Robinson, J. D. Black, J. M. Benedetto, and P. H. Eaton, Effects of guard bands and well contacts in mitigating long SETs in advanced CMOS processes, [J], IEEE Trans. Nucl. Sci., 2008 55 (3) 1708-1713.

DOI: 10.1109/tns.2008.920260

Google Scholar

[9] J. D. Black, A. L. Sternberg, M. L. Alles, A. F. Witulski, B. L. Bhuva, L. W. Massengill, J. M. Benedetto, M. P. Baze, J. L. Wert, and M. G. Hubert, HBD layout isolation techniques for multiple node charge collection mitigation, [J], IEEE Trans. Nucl. Sci., 2005 52 (6) 2536-2541.

DOI: 10.1109/tns.2005.860718

Google Scholar

[10] B. Narasimham, J. W. Gambles, R. L. Shuler, B. L. Bhuva, and L. W. Massengill, Quantifying the effect of guard rings and guard drains in mitigating charge collection and charge spread, [J], IEEE Trans. Nucl. Sci., 2008 55 (6) 3456-3460.

DOI: 10.1109/tns.2008.2007119

Google Scholar

[11] J. R. Ahlbin, M. J. Gadlage, N. M. Atkinson, B. Narasimham, B. L. Bhuva, A. F. Witulski, W. T. Holman, P. H. Eaton, and L. W. Massengill, Effect of multiple-transistor charge collection on single-event transient pulse widths, [J], IEEE Trans. Device Mater. Rel., 2011 11 (3) 401-406.

DOI: 10.1109/tdmr.2011.2157506

Google Scholar

[12] S. Dasgupta, O. A. Amusan, M. L. Alles, A. F. Witulski, L. W. Massengill, B. L. Bhuva, R. D. Schrimpf, and R. A. Reed, Use of a contacted buried n+ layer for single event mitigation in 90 nm CMOS, [J], IEEE Trans. Nucl. Sci., 2009 56 (4) 2008-(2013).

DOI: 10.1109/tns.2008.2012344

Google Scholar

[13] J. J. Chen, S. M. Chen, B. Liang, and B. W. Liu, Simulation study of the layout technique for P-hit single-event transient mitigation via the source isolation, [J], IEEE Trans. Device Mater. Rel., 2012 12 (2) 501-509.

DOI: 10.1109/tdmr.2012.2191971

Google Scholar

[14] G. Li, Buried layer substrate isolation in integrated circuits, U.S. Patent No. 6, 831, 346, (2004).

Google Scholar

[15] B. D. Olson, D. R. Ball, K. M. Warren, L. W. Massengill, N. F. Haddad, S. E. Doyle, and D. McMorrow, Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design, [J], IEEE Trans. Nucl. Sci., 2005 52 (6) 2132- 2136.

DOI: 10.1109/tns.2005.860684

Google Scholar

[16] P. E. Dodd, M. R. Shaneyfelt, and F. W. Sexton, Charge collection and SEU from angled ion strikes, [J], IEEE Trans. Nucl. Sci., 1997 44 (6) 2256-2265.

DOI: 10.1109/23.659044

Google Scholar