A High-Performance Sigma-Delta Modulator in 0.18μm CMOS Technology

Abstract:

Sigma-Delta (∑∆) modulators are commonly used in high-resolution analog-to-digital converters (ADCs). In this paper, a high-performance modulator targeted for ultra-high-frequency (UHF) radio-frequency identification (RFID) zero-intermediate frequency (ZIF) receivers is designed in standard 0.18μm CMOS technology. The modulator has been designed with switched-capacitor (SC) integrators employing gain-boosted operational amplifiers, voltage comparators and nonoverlapping clock generators to satisfy such requirements as high gain, low voltage and wide bandwidth. The behavioral-level modeling and circuit-level design are carried out with MATLAB/Simulink and Cadence/SpectreRF, respectively. Ultimately, the high-speed and low-power realization of a second-order single-bit modulator with an oversampling ratio (OSR) of 32 is presented. Simulation results shown that, from a 1.8V supply, operated at a sampling frequency of 64MHz, a dynamic range of 53.4dB over a signal bandwidth of 1MHz is achieved.

• Periodical: Applied Mechanics and Materials (Volumes 519-520)
• Pages: 1085-1088
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.519-520.1085
• Online since: February 2014
• Authors: Ying Qi Qian, Chang Chun Zhang, Zhong Chao Liu, Lei Lei Liu, Yu Rong Luan, Yu Ming Fang, Yu Feng Guo
• Keywords: Gain-Boosted, Nonoverlapping Clock, Sigma-Delta (∑∆) Modulator, Switched-Capacitor (SC) Integrator

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