Digital Test System Design and Realization Based on DDR3

Abstract:

Based on the current international trends in technology of the memory controller, a DDR3 memory controller design plan, the program will be the function of the storage controller further divided into the transport layer and the physical layer, followed by the main module functions and the implementation details are described in detail. The controller can efficiently complete the memory request scheduling, increase the memory bus utilization, thereby improving the memory access bandwidth and reduces memory access latency to provide some reference in the future other support for DDR3 memory digital system design. The final completion of DDR3-based digital test system, the input parallel digital signal judgment, the judgment of data stored in the DDR3 memory and the destination address data read out the analysis.

• Periodical: Applied Mechanics and Materials (Volumes 543-547)
• Pages: 1128-1131
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.543-547.1128
• Online since: March 2014
• Authors: Tao Yue*
• Keywords: DDR3, Digital Test System, FPGA, Simulation to Achieve, Timing Control

References

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[2] Information on http: /baike. baidu. com/view/1191. htm.

[3] JEDEC DDR3 SDRAM Specification, JESD79-3E, (2010).

[4] Kevin Guo: Memory Basic Concept and Major Feature, (2008).