Power Optimization in Domino Circuits Using Current Mirror Based Leakage Compensating Keeper

Abstract:

In this work low leakage and high noise immunity domino circuit with negligible speed degradation is proposed. Wide Fan-In Gates are widely used as address decoders in memories. Wide Fan-In Gates increase the capacitance of the dynamic node which reduces the speed in domino circuits. Current contention exists between keeper transistor and evaluation network adding to speed reduction. To overcome this problem logic implementation network in the proposed Leakage Compensating Keeper (LCK) is separated from the dynamic node by current comparison stage in which the current of the pull up network is used to charge the capacitor at the dynamic node. Since capacitance is reduced the loss in speed due to additional transistors is compensated. Because of reduced parasitic capacitance Current Mirror based LCK is enough to design faster circuits. LCK improves the noise immunity by grounding the pull up networks leakage current. Simulation results shows that the proposed circuit has 22% power reduction compared to Standard Footless Domino for a 64bit input OR gate.

• Periodical: Applied Mechanics and Materials (Volume 573)
• Pages: 169-175
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.573.169
• Online since: June 2014
• Authors: Karthikeyan Perumal*, R. Saravanan, N. Saravanan
• Keywords: Domino Circuits, Leakage Compensating Keeper (LCK), Pull-Down Network (PDN), Pull-Up Network (PUN), Threshold Voltage (Vth)

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