Design and Implementation of High-Speed Clock Recovery Circuits Based on FPGA

Abstract:

According to the problem that the traditional clock recovery method based on FPGA can not recover the clock of higher frequency NRZ (Non-return to zero) serial data. This paper proposed a clock recovery design that adjusts the output clock earlier or later constantly according to the phase relationship between the input data and the feedback clock. The proposed design can be implemented on the FPGA without the higher operating frequency requirement meets the demand of middle and low version FPGA clients. The circuits implemented on FPGA has been downloaded to the Xilinx Virtex5 XC5VSX50T FPGA after behavioral simulation and post-route simulation, the debugging results verified that the proposed design is effective and realizable for clock recovery of higher frequency NRZ data and realizable for FPGA.

• Periodical: Applied Mechanics and Materials (Volumes 602-605)
• Pages: 2586-2589
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.602-605.2586
• Online since: August 2014
• Authors: Xiu Li Du*, Cun Da Chu, Shao Ming Qiu
• Keywords: Clock Recovery, Feedback Clock, FPGA, Serial Communication

References

[1] Chunmao Liu, Zhifei Yang, Xiaopan Wang, Weitong Jin. The design of clock and data recovery circuits based on Virtex-Ⅱ. Science Technology and Engineering. 2010. 7. 5287-5290.

[2] Wei Qv, Zhian Sun. The implementation method of high-speed serial link data's recovery based on FPGA. Computer Measurement and Control. 2011. 19(1). 219-221.

[3] Xuan Wang, Jun Du. A method of he clock synchronization and implement of CE/PTN[J]. Communications technology. 2009, 42(02): 88-90.

[4] Changchun Zhang, Zhigong Wang, Yufeng Guo, Si Si. The study of high-speed clock and data recovery circuits technology. Circuits and Systems. 2012. 6: 60-65.

[5] Quanhui Ren, Yuhong Zhao. The design of clock and data recovery circuits based on FPGA. The journal of Zhengzhou Railway vocational and technical College. 2011. 26-28.

[6] Xiangqiong Li, Qijun Huang, Sheng Chang. The implementation of high-speed clock and data recovery circuits based FPGA. Electronic Technology. 48-50.

[7] Milan Forcan. Concept Creation and Design of a Parameterizable, fast-locking 65 nm CMOS CDR-PLL for Gigabit Serial Chip-to-Chip Communication in Mobile Devices.

[8] Special Topics in High-Speed Links Circuits and Systems Spring. 2010. Lecture 30: CDRs.

[9] Johnson E E. Performance Envelope Of Broadrand HF Data Waveforms, (2009).

[10] Shaochun Ning. The design and FPGA implementation of data recovery circuits for a low-cost optical receiver. Electron mass. 2012. 04th. 26-28.