Design and Implementation of RS Encoder and Decoder in OFDM System Based on FPGA

Guang Hui Cai; Shu Wen Zheng; Ping Li; Chuan Liang

doi:10.4028/www.scientific.net/AMM.602-605.2619

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 602-605Design and Implementation of RS Encoder and...

Design and Implementation of RS Encoder and Decoder in OFDM System Based on FPGA

Abstract:

This paper introduces the basic principle of RS codes in OFDM system and the design method of 16 shift registers, finite field multiplicators and adders, on and timing circuit are validated by using of EDA tools Quartus II. Finally, the simulation results is given and demonstrates that a good channel encoding and decoding can be achieved by using FPGA in OFDM system, which can save the cost, shorten the designing cycle , and is convenient to speed up the listing of products, occupy less hardware resources, and comply with the development trend of modern communication.

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Periodical:

Applied Mechanics and Materials (Volumes 602-605)

Pages:

2619-2622

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.602-605.2619

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Online since:

August 2014

Authors:

Guang Hui Cai*, Shu Wen Zheng, Ping Li, Chuan Liang

Keywords:

FPGA, Ip Core, OFDM, Rs Code

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* - Corresponding Author

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