A High Rate Parallel Operation Encryption Card Design Base on FPGA

Rong Zeng; Xiu Li Huang; Ya Dong Chen

doi:10.4028/www.scientific.net/AMM.668-669.783

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 668-669A High Rate Parallel Operation Encryption Card...

A High Rate Parallel Operation Encryption Card Design Base on FPGA

Abstract:

A design of encryption cards controlling multiple cipher chips’ high-rate parallel operation based on FPGA is proposed in this paper. According to the design method, we can achieve that multiple encryption card operates encryption in parallel way, which can improve the encryption and decryption rate of the encryption card without enhancing the performance of encryption chip, moreover, increase the key generation rate and management level of the key management system.

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Periodical:

Applied Mechanics and Materials (Volumes 668-669)

Pages:

783-786

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.668-669.783

Citation:

Cite this paper

Online since:

October 2014

Authors:

Rong Zeng, Xiu Li Huang, Ya Dong Chen

Keywords:

Data Encryption, Encryption Card, FPGA, Parallel Encryption

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References

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