FPGA Based Frequency Correction of Master Clock Terminals of Whole-View Test Systems

Bi Lu Luo; Qi Huang; Li Yue Cao; San Gen Yang; Xiao Dong Hu

doi:10.4028/www.scientific.net/AMM.668-669.830

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 668-669FPGA Based Frequency Correction of Master Clock...

FPGA Based Frequency Correction of Master Clock Terminals of Whole-View Test Systems

Abstract:

Aiming at the problem of low accuracy and insufficient stability of master clock terminals frequency in Whole-view Test Systems, in this paper, a simple and effective method to Correct frequency of OCXO (Oven Controlled Crystal Oscillator) have been proposed. This approach based on the principle of establishing time system within FPGA, with TDC (Time to Digital Converter) measure the periodic deviation between OCXO and GPS, modifying the value of period within FPGA, reaching the purpose of frequency correction. To reduce the impact of GPS signal jitter, the moving average filter algorithm has been used to tame OCXO quickly. Through simulations and experiments, the clock frequency accuracy is higher than the average 5×10^-10, and the time accuracy is better than 1.8μ/h.

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Periodical:

Applied Mechanics and Materials (Volumes 668-669)

Pages:

830-835

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.668-669.830

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Online since:

October 2014

Authors:

Bi Lu Luo*, Qi Huang, Li Yue Cao, San Gen Yang, Xiao Dong Hu

Keywords:

FPGA, Oven Controlled Crystal Oscillator, Period Counter, Time-To-Digital Converter

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* - Corresponding Author

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