An Advanced Verification Platform Based on UVM

Abstract:

An advanced verification platfrom based on UVM architecture is implemented in this paper. This paper presents a hierarchical verification environment that is portable, reusable, and easy to extend, which is constructed based on an object oriented language named System Verilog. The verification platform is applied to verify a RFID (Radio Frequency Identification) tag chip which is compliant with the ISO/IEC15693 standard, communicates with a reader outside through a RF analog circuitry, completes anti-collision flow, selects card, authenticates based on SM7 algorithm and controls the writing and reading of EEPROM inside. According to the instruction supported by the tag chip is wide and variety, and further more it’s very rich in the command frame contents, the advanced verification platform which achieves the constraint-random stimulus generation, functional coverage and self-check mechanism, reduces the verification cycle, improves verification efficiency and ensures verification adequacy.

• Periodical: Applied Mechanics and Materials (Volumes 670-671)
• Pages: 1441-1446
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.670-671.1441
• Online since: October 2014
• Authors: Jing Wang, Fei Wang
• Keywords: Constraint-Random, Functional Coverage, ISO/IEC 15693, Radio Frequency, Universal Verification Methodology (UVM), Verification Platform

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