Simulation and Analysis of DDR3 Bus Based on Fly-By Topology with Cadence

Abstract:

For the requirements of different bus signals from high speed PCB with DDR3 components based on fly-by topology structure, coping strategies have been proposed respectively. For the address or command bus, a leveling-free strategy has been proposed. It shows that the phase difference can be nearly zero through reasonable constraints on PCB design. The strategy was applied to the clock bus and achieved good performance, combining with the rules of signal integrity. For the data bus, the timing sequence on source synchronous has been analyzed and the time margin was calculated. The reasonability of the design was verified through the simulation result with Cadence.

• Periodical: Applied Mechanics and Materials (Volumes 670-671)
• Pages: 1447-1453
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.670-671.1447
• Online since: October 2014
• Authors: Bao Po Wang, Jin Song Du, Xing Tian, Xin Bi*
• Keywords: DDR3, Fly-By, Leveling-Free, PCB Design, Source Synchronous

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