A Segmented DCDL Based on Gate Delay and Phase Interpolation

Xian Jie Wan; Jun Liu; Guang Bing Chen; Yu Xin Wang; Dong Bing Fu

doi:10.4028/www.scientific.net/AMM.687-691.3158

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 687-691A Segmented DCDL Based on Gate Delay and Phase...

A Segmented DCDL Based on Gate Delay and Phase Interpolation

Abstract:

The IC technology of adjustable delay is simply presented. Then aim at the engineering application forms a kind of segmented Digitally Controlled Delay Line (DCDL) which has overcame the tradeoff between adjustable delay resolution and dynamic range, benefited from small die area, high resolution and large adjustable range. Finally presented is the performance of the segmented DCDL which is fabricated by 0.18μm CMOS technology. From the test result, the DCDL’s resolution is 12ps and the dynamic range is 4ns.

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Periodical:

Applied Mechanics and Materials (Volumes 687-691)

Pages:

3158-3161

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.687-691.3158

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Online since:

November 2014

Authors:

Xian Jie Wan*, Jun Liu, Guang Bing Chen, Yu Xin Wang, Dong Bing Fu

Keywords:

DCDL, Phase Interpolation, Tri-State Inverter

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* - Corresponding Author

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