A Capacitor Memory Erasing Technique for Pipeline ADCs

Ai Guo; Rong Bin Hu

doi:10.4028/www.scientific.net/AMM.687-691.3285

Paper Titles

Control of Grid-Connected Quasi-Z Source Inverter Based on Three-States Constant Frequency Hysteresis Current Control
p.3266

A New Fast Filtering Algorithm Based on Multiple Digital Sampling Rate Conversion
p.3270

On Study of Harmonic Load Modeling for Equipment Power System
p.3276

Solar LED Intelligent Lighting Systems Based on Internet of Things and New Energy Storage System
p.3281

A Capacitor Memory Erasing Technique for Pipeline ADCs
p.3285

Study on Visualization of Large Consumers' Operational Risk Information in Power Supply Company
p.3289

Power Grid Vulnerability Research Based on the Comprehensive Parameter
p.3294

Chip Waveforms Attribute Recognition Model Research and Design
p.3299

Modeling and Analysis of the Operational Amplifier with SC Circuit
p.3304

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 687-691A Capacitor Memory Erasing Technique for Pipeline...

A Capacitor Memory Erasing Technique for Pipeline ADCs

Abstract:

A capacitor memory erasing technique for pipeline ADC is introduced, which insert a clearing phase to the traditional working timing sequence of the MDAC to erasing the residual charges on the sampling capacitor. The measurement shows that the 14-bit pipeline ADC adopting the proposed technique can achieve a sampling rate of 250MSPS with SNR 69dB, SFDR 80dB, compared with the traditional ADC of sampling rate 100MSPS, SNR 60dB, SFDR 71dB, which proves the proposed technique can improve the performances of pipeline ADCS obviously.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 687-691)

Pages:

3285-3288

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.687-691.3285

Citation:

Cite this paper

Online since:

November 2014

Authors:

Ai Guo*, Rong Bin Hu

Keywords:

Capacitor Memory Erasing, MDAC, Pipeline ADC, Switch

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] E. Siragusa and I. Galton A digitally enhanced 1. 8 V 15-bit 40-MSample/s CMOS pipelined ADC, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp.2126-2138 (2004).

DOI: 10.1109/jssc.2004.836230

Google Scholar

[2] P. Wu , V. Luen and H. Luong A 1 V 100-MS/s 8 bit CMOS switched- opamp pipelined ADC using loading free architecture, IEEE J. Solid-State Circuits, vol. 42, no. 4, pp.730-738 (2007).

DOI: 10.1109/jssc.2007.891666

Google Scholar

[3] B. Min , P. Kim , F. W. Bowman III, D. M. Boisvert and A. J. Aude A 69 mW 10-bit 80-MSample/s pipelined CMOS ADC, IEEE J. Solid-State Circuits, vol. 38, no. 12, pp.2031-2039 (2003).

DOI: 10.1109/jssc.2003.819166

Google Scholar

[4] D. Kurose , T. Ito , T. Ueno , T. Yamaji and T. Itakura 55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers, IEEE J. Solid-State Circuits, vol. 41, no. 7, pp.1589-1595 (2006).

DOI: 10.1109/jssc.2006.873888

Google Scholar

[5] J. Yuan , N. Farhat and J. Van der Spiegel Background calibration with piecewise linearized error model for CMOS pipeline A/D converter, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 1, pp.311-321 (2008).

DOI: 10.1109/tcsi.2007.910645

Google Scholar

[6] B. Lee , B. Min , G. Manganarom and J. W. Valvano A 14-b 100-MS/s pipelined ADC with a merged SHA and first MDAC, IEEE J. Solid- State Circuits, vol. 43, no. 12, pp.2613-2619 (2008).

DOI: 10.1109/jssc.2008.2006309

Google Scholar

[7] I. Ahmed, Pipelined ADC Design and Enhancement Techniques, Springer Science+Business Media, (2010).

Google Scholar