Design and Implementation of FPGA-Based JPEG Decoding IP Core and its Application in Digital Watermarking

Qun Xiu Yu; Shou Ming Zhang; Chao Wang; Li Zhi Xie

doi:10.4028/www.scientific.net/AMM.734.621

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 734Design and Implementation of FPGA-Based JPEG...

Design and Implementation of FPGA-Based JPEG Decoding IP Core and its Application in Digital Watermarking

Abstract:

In this paper the digital watermarking algorithm deep into the field of integrated circuits combined with the JPEG image watermarking processes and SOPC technology, Verilog HDL language is used to design and implement of a reusable JPEG decoder IP core which can be embedded, realizing the JPEG decoding on FPGA platform and further completing the watermark embedding. The JPEG decoder is tested through the Modalism simulation software and would be revised until the simulation results become correct. Finally, the Altera development board EP2C70F896C6N of CycloneII series is used to complete the system design. The results prove that the system can run well, the program which can obtain a larger increase speed in exchange for consuming a little hardware resource does work.

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Periodical:

Applied Mechanics and Materials (Volume 734)

Pages:

621-624

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.734.621

Citation:

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Online since:

February 2015

Authors:

Qun Xiu Yu, Shou Ming Zhang*, Chao Wang, Li Zhi Xie

Keywords:

FPGA, Ip Core, JPEG Decode, Speed, Watermark

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* - Corresponding Author

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