Review of Single Cycle Shifter for Structured LDPC Encoder

Abstract:

Shifter has been used in encoder of structured low density parity check (LDPC) codes due to the nature of its structure. Single clock cycle time of shifter is selected for doing matrix-vector multiplication of LDPC encoding to minimize encoding latency. Among the shifters which complete the multiplication within one clock cycle, this paper suggests the cyclic shifter for structured LDPC encoder. It is shown that the implementation of the typical cyclic shifter has less logic gates and less bit controller than the other shifter.

• Periodical: Applied Mechanics and Materials (Volume 763)
• Pages: 189-194
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.763.189
• Online since: May 2015
• Authors: Silvia Anggraeni*, Fawnizu Azmadi Hussin, Varun Jeoti
• Keywords: Cyclic Shifter, Encoding, Structured LDPC

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