Optimization of Holding Voltage for 5V Multi-Finger NMOS Using Voltage Stepping Simulation

Aryadeep Mrinal; Gene Sheu; Shao Ming Yang; Aunny Kant Sharma; Jun Bo Wang; Mohammad Amanullah

doi:10.4028/www.scientific.net/AMM.764-765.526

Paper Titles

High Pumping Gain Dickson Charge Pump Using Improved Bootstrapped Technique
p.506

Hybrid Analog/Digital Modulations Using Polarization Multiplexing OCDMA Scheme in Free Space Optics
p.511

Impact of Parasitic Capacitor to the GaN HEMT Devices
p.515

Improvement of On-Resistance Degradation Induced by Hot Carrier Injection in SOI-LDMOS
p.521

Optimization of Holding Voltage for 5V Multi-Finger NMOS Using Voltage Stepping Simulation
p.526

Simulation of P-Type Doping Profile Prediction Using Different Ion Implantation and Diffusion Model
p.530

Unambiguous Composite BOC Signal Tracking Based on Partitioned Sub-Carriers
p.535

Using GaN-Si FET Cascode Switches for Improving the Light-Load Efficiency of LLC Converters
p.540

Using Wavelet Hybrid Self-Organizing Feature Map Network for V-I Based Multiple Harmonic Sources Classification
p.545

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 764-765Optimization of Holding Voltage for 5V...

Optimization of Holding Voltage for 5V Multi-Finger NMOS Using Voltage Stepping Simulation

Abstract:

For IC component designs, ESD is one of an important issue which has to be taken in consideration for reliability of a device. We use the TLP Voltage Stepping simulation scheme in Medici simulation for 5V NMOS Multi-finger structure, the use of silicon model and set of variables, in silicon material parameter is used to vary the variable electron and hole parameters of silicon, which can make the Holding Voltage simulation change and to make the simulation and the silicon data more consistent. We have simulated and calibrated Holding voltage of 5V NMOS multi finger to match with silicon data.

You might also be interested in these eBooks

Modern Design Technologies and Experiment for Advanced Manufacture and Industry

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 764-765)

Pages:

526-529

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.764-765.526

Citation:

Cite this paper

Online since:

May 2015

Authors:

Aryadeep Mrinal, Gene Sheu, Shao Ming Yang*, Aunny Kant Sharma, Jun Bo Wang, Mohammad Amanullah

Keywords:

ESD, Holding Voltage, MEDICI, Multi-Finger, NMOS, Silicon Material Parameter, TLP, Voltage Stepping Simulation

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] M. Heer, S. Bychikhin , V. Dubec, D. Pogany, E. Gornik, M. Dissegna,L. Cerati, L. Zullino, A. Andreini, A. Tazzoli, G. Meneghesso: 2006, Analysis of the triggering behavior of low voltage BCD single and multi-finger gc-NMOS ESD protection devices.

DOI: 10.1109/ispsd.2006.1666146

Google Scholar

[2] L. Sponton, L. Cerati, G. Croce, F. Chrappan, C. Contiero, G. Meneghesso and E. Zanoni: ESD protection structure for BCD5 smart power technology, in Microel. Reliab., vol. 41, 2001 , pp.1683-1687.

DOI: 10.1016/s0026-2714(01)00188-3

Google Scholar

[3] A. Amerasekera, C. Duvvury: ESD in silicon integrated circuitc, Wiley, Chichester, (1995).

Google Scholar

[4] Yu-Chul Hwang Doctor of Philosophy, 2004, Electrostatic discharge and electrical overstress failures of non-silicon devices.

Google Scholar

[5] M. Valdinoci, D. Ventura, M.C. Vecchi, M. Rudan, G. Baccarani, F. Illien', A. Stricker', L. Zullinob: Impact-ionization in silicon at large operating Temperature.

DOI: 10.1109/sispad.1999.799251

Google Scholar

[6] Synopsis Taurus Medici User Guide Version D-2010. 03, March 2010, Synopsys Inc., Mountain View, (2010).

Google Scholar