Improvement of On-Resistance Degradation Induced by Hot Carrier Injection in SOI-LDMOS

Abstract:

This paper presents how to improve specific o n-state resistance (Ron) induced by the HCI of a SOI LDMOS device. In manufacturing of UHV device, trade-off between on state resistance and breakdown voltage is always present. But with our process design we are able to improve Ron degradation without compromising the-breakdown voltage. In our design the peak electric field is under gate near source side, due to low electric field near drain helps to increase the current flow much better hence it helps to improve Ron and Vth. If the peak field is located near drain side, the hot holes is easy to penetrate to field oxide and avoid current flow then it causes increase in the Ron.Our simulation results shows 0.27% and 0.95% Ron and Vth increases respectively even at 1e5 second stress time .The Ron degradation phenomenon was analyzed with the 2-D simulation of electric field and impact ionization generation.

• Periodical: Applied Mechanics and Materials (Volumes 764-765)
• Pages: 521-525
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.764-765.521
• Online since: May 2015
• Authors: Vivek Ningaraju, Shao Ming Yang*, Gene Sheu, Mohammad Amanullah, Erry Dwi Kurniawan, Subramanyaj Subramanyaj
• Keywords: HCI, Interface Trap, Ron, SOI, Stress Time

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