1-D Integer Transform for HEVC Encoder Using DSP Slices on FPGA

Pancheewa Arayacheeppreecha; Suree Pumrin; Boonchuay Supmonchai

doi:10.4028/www.scientific.net/AMM.781.151

Paper Titles

Internet Cigarette and Tobacco Business (ICTB) Database for Domestic Markets in Thailand
p.133

Development of Embedded Simple Network Time Protocol Client Clock
p.137

Performance of Interworking Proxy for Interconnecting IEEE1888 Standard at ETSI M2M Platforms
p.141

Android Antivirus Scanner by Analyzing Operation Codes
p.145

1-D Integer Transform for HEVC Encoder Using DSP Slices on FPGA
p.151

Voltage-Mode Multifunctional Biquadratic Filter Using VDDDA
p.155

Yield Analysis Based on the Defect Analysis with Derivative Method
p.160

The Effect of Anode Width of Dual Schottky Magnetodiode to Sensitivity
p.164

CMOS-Based Current-Mode Elliptic Ladder Band-Pass Filter
p.168

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 7811-D Integer Transform for HEVC Encoder Using DSP...

1-D Integer Transform for HEVC Encoder Using DSP Slices on FPGA

Abstract:

This paper presents an FPGA architecture for the 1-D integer transform of the latest video coding standard, the High Efficiency Video Coding (HEVC). The design employs hard multipliers in dedicated DSP slices, which are already embedded into an FPGA die, to gain high throughput and save general purpose LUTs. The proposed architecture can support 4x4, 8x8, 16x16, and 32x32 transform. A multiplier sharing scheme is introduced to reduce the total number of required DSP slices in order to be able to fit the design onto a Spartan-3A FPGA. The design can reach a maximum throughput of 1,692 Msamples/s irrespective of the transform size, which is enough to encode 8K (7680x4320) videos at 30 fps. This work is a pioneer research that utilizes the dedicated multipliers on FPGAs in the design of the HEVC transform.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volume 781)

Pages:

151-154

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.781.151

Citation:

Cite this paper

Online since:

August 2015

Authors:

Pancheewa Arayacheeppreecha*, Suree Pumrin, Boonchuay Supmonchai

Keywords:

Architecture, Field Programmable Gate Array (FPGA), High Efficiency Video Coding (HEVC), Integer Transform, Video Coding

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] G. J. Sullivan, J. -R. Ohm,W. -J. Han, and T. Wiegand, Overview of the high efficiency video coding (HEVC) standard, IEEE Trans Circuits Syst. Video Technol. 22 (2012) 1649-1668.

DOI: 10.1109/tcsvt.2012.2221191

Google Scholar

[2] S. Y. Park, and P. K. Meher, Flexible integer DCT architectures for HEVC, IEEE International Symposium on Circuits and Systems (ISCAS) (2013) 1376-1379.

DOI: 10.1109/iscas.2013.6572111

Google Scholar

[3] W. Zhao, T. Onoye, and T. Song, High-performance multiplierless transform architecture for HEVC, IEEE International Symposium on Circuits and Systems (ISCAS) (2013) 1668-1671.

DOI: 10.1109/iscas.2013.6572184

Google Scholar

[4] P. K. Meher, S. Y. Park, B. K. Mohanty, K. S. Lim, and C. Yeo, Efficient Integer DCT Architecture for HEVC, IEEE Trans Circuits Sys. Video Technol. 24 (2014) 168-178.

DOI: 10.1109/tcsvt.2013.2276862

Google Scholar

[5] R. Jeske, J. C. Souza , G. Wrege , R. Cenceicao, M. Grellert, J. Mattos, and L. Agostini, Low Cost and High Throughput Multiplierless Design of a 16p 1-D DCT of the New HEVC Video Coding Standard, VIII Southern Conference on Programmable Logic (SPL) (2012).

DOI: 10.1109/spl.2012.6211786

Google Scholar

[6] A. Fuldseth, G. Bjontegaard, M. Budagavi, and V. Sze, CE10: Core transform design for HEVC, JCTVC-G495. (2011).

Google Scholar

[7] Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11, HM Software Version 13. 0.

Google Scholar

[8] Xilinx Inc, Spartan-3A DSP FPGA Family Data Sheet, DS610. (2010).

Google Scholar