Yield Analysis Based on the Defect Analysis with Derivative Method

Warakorn Praepattharapisut; Weera Pengchan; Toempong Phetchakul; Amporn Poyai

doi:10.4028/www.scientific.net/AMM.781.160

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 781Yield Analysis Based on the Defect Analysis with...

Yield Analysis Based on the Defect Analysis with Derivative Method

Abstract:

This paper presented the corresponding between the yield equation prediction from Poisson, Murphy with wafer actual yield on the silicon wafer with 0.8 μm CMOS technology. The defect analysis with derivative method, current - voltage and capacitance-voltage of diode characteristic measurement, is used to define the defect in p-n junction on silicon wafer. The different sampling numbers of chips are used to calculate the yield. Finally the calculated data and actual would be compared and found that at sampling number is 25, the tolerance from actual yield is less than 3%.

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Periodical:

Applied Mechanics and Materials (Volume 781)

Pages:

160-163

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.781.160

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Online since:

August 2015

Authors:

Warakorn Praepattharapisut, Weera Pengchan*, Toempong Phetchakul, Amporn Poyai

Keywords:

CMOS Technology, Defect, Gerenation Lifetime, p-n Junction, Recombination Lifetime, Yield Model

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* - Corresponding Author

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