The Potential of Routers Configured with the Switch Matrix by RTL

Tomoaki Sato; Sorawat Chivapreecha; Phichet Moungnoul

doi:10.4028/www.scientific.net/AMM.781.189

Paper Titles

Effect of MgO Barrier Thickness with Tilted Magnetization on Temperature Increase in Magnetic Tunnel Junction Devices during Current-Induced Magnetization Switching
p.172

On the Realization of CMOS Current-Controlled Current Conveyor Transconductance Amplifier (CCCCTA) with Linear Control of g_m
p.176

A Simple Fully Controllable Schmitt Trigger with Electronic Method Using VDTA
p.180

DSSCs Fabrication Using Nano-Structured Titania as Photoanode
p.184

The Potential of Routers Configured with the Switch Matrix by RTL
p.189

Free Layer Characterization of TMR Head with Multi-Stripe Height by Using Ferro Magnetic Resonance Analyzer (FMRA)
p.195

Study the Effect of Stripe Height and Read Track Width on Blocking Temperature
p.199

Signal Analysis of Scratch-Detection on Magnetic Disc by Using Light Reflection Approach
p.203

Effects of Magnetic Properties of L1₀-CoPt based Bit Patterned Media with Tilted-Easy Axis on Switching Field at Areal Density over 2 Tb/in²
p.207

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 781The Potential of Routers Configured with the...

The Potential of Routers Configured with the Switch Matrix by RTL

Abstract:

In this paper, analysis results of an FPGA (Field-Programmable Gate Array) designed in RTL (Register Transfer Level) shows that does not have a problem in routing. It has many advantages than conventional FPGA developed by the transistor level. However, the crossbar switch of the FPGA designed in RTL has a problem with the direction of the signal. The direction is fixed in one direction unlike the conventional crossbar switch. Routing is analyzed by using the circuit of three input two output.

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Periodical:

Applied Mechanics and Materials (Volume 781)

Pages:

189-192

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.781.189

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Online since:

August 2015

Authors:

Tomoaki Sato*, Sorawat Chivapreecha, Phichet Moungnoul

Keywords:

FPGA, Full Adder, Route Configuration, RTL, Switch Matrix

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* - Corresponding Author

References

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