Reconfigurable Boundary Scan Tester Using Cellular-Automata Register Technology

Abstract:

In this paper we reconfigure the input boundary-scan register to an operable test pattern generator that provides test patterns to the logic circuit for a predetermined number of clock cycles upon receipt of the built-in self-test control signal. The output boundary-scan register is reconfigurable to operate as an output response analyser that is driven by the logic circuit for the predetermined number of clock cycles upon receipt of the built-in self-test control signal. A family of input and output boundary-scan cells that can be reconfigured as a linear feedback shift register and as a multiple-input shift register is disclosed.

• Periodical: Advanced Materials Research (Volumes 1006-1007)
• Pages: 986-989
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.1006-1007.986
• Online since: August 2014
• Authors: Kai Bei Peng*, Jin Tao Zhang
• Keywords: Boundary Scan, Build in Self-Test, TAP Controller

References

[1] F. Beenker and C. Maunder, Boundary-Scan, A Framework for Structured Design-For-Test, " Proc, Int, l Test Conf., Sept. 1987, pp.724-729.

[2] C. Maunder, F. Beenker, and C. Vivier. A Standard Boundary Scan Architecture Version 1. 0. June (1987).

[3] STAG. Boundary-Scan Architecture Standard Proposal Version 2. 0, Mar. (1988).

[4] JOSÉ M. MIRANDA. A BIST and Boundary-Scan Economics Framework., Design & Test of Computers, IEEE, Jul-Sep 1997, Vol. 13 pp.17-23.

DOI: 10.1109/54.605988

[5] C. Tsai, F. Guo, and J. Hong. IEEE STD. 1149. 1 Boundary scan circuit capable of Built-In Self-Testing., United States Patent No. 5, 570, 375. Oct. 29, 1996, pp.1-5.

[6] C. Maunder and E. Tullos, The Test Access Port And Boundary-Scan Architecture. IEEE Computer Society Press, Los Alamitos, California. 1992. Pp. 23-27.

[7] C. Tsai, F. Guo, and J. Hong. IEEE STD. 1149. 1 Boundary scan circuit capable of Built-In Self-Testing., United States Patent No. 5, 570, 375. Oct. 29, 1996, pp.1-5.

[8] R. Burgess, P. Nagaraj, and M.N. Waseq The boundary scan, Potentials, IEEE, Vol 14 Aug/Sep 1995, Virginia Univ., Charlottesville, VA. pp.11-12.

DOI: 10.1109/45.464687

[9] C. Gloster and F. Brglez. Integration of Boundary Scan with Cellular-Based Built-In Self-Test for Scan-Based Architectures, Version 1. 0, tech. rpt. TR87- 18, Microelectronics Center of North Carolina, Research Triangle Park, New York. Aug. (1987).

DOI: 10.1109/test.1988.207791

[10] Texas Instruments, Built-In Self-Test (BIST) Using Boundary Scan, Dec. (1992).

[11] H. William, Paul McAnney, H. Bardel, l and Jacob Savir. Built-In Test for VLSI: Pseudorandom Techniques. John Wiley and Sons, Inc., New York, (1987).

[12] S. Clay and Franc Brglez, Boundary Scan with Built-In Self-Test, IEEE Design & Test Vol. 6 January 1989. IEEE Computer Society Press Los Alamitos, CA, USA.

DOI: 10.1109/54.20388

[13] F. Beenker. Systematic and Structured Methods for Digital Board Testing, Proceedings IEEE International Test Conference, 1985, p.380–385.