A Low Noise CMOS Digital Output Interface Circuit

Abstract:

A digital CMOS output interface circuit is proposed, which lowers down the peak and lengthen the duration of the pulse of current supplied by the power supply to reduce the SSN (simultaneously-switching noise) effects. The simulation shows that the maximal SSN voltage of the proposed circuit is 331.5mV compared to 662.4mV of the traditional one.

• Periodical: Advanced Materials Research (Volumes 1049-1050)
• Pages: 653-656
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.1049-1050.653
• Online since: October 2014
• Authors: Hua Xu*, Zhe Qiao
• Keywords: CMOS, Driving Circuit, Interface, Package, SSN

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