Paper Titles

Current-Voltage Characterization of Gallium Arsenide Nanowires Using a Conductive Atomic Force Microscopy
p.238

Controlled Growth of WO₃-Loaded TiO₂ Nanotubes for Tandem Solar-Driven Water Splitting Cell
p.243

Catalytic Oxidation of Alkyl Benzene
p.248

Morphological and Electrical Properties of Silicon Dioxide-Based Interdigitated Electrode Arrays
p.253

Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs on Suppression of Short-Channel Effects (SCEs): A Review
p.257

The Influence of Wafer Cleaning Process on the Silicon Surface Roughness
p.262

Synthesis of Al-Doped ZnO Nanorod Arrays on Al-Doped ZnO Seed Layer and their Properties
p.266

Preparation and Characterization of Pt Coated on Al-Doped ZnO Nanorods Thin Film at Different Thicknesses
p.271

Physical and Electrical Properties of Nano-Structured Sn-Doped Zinc Oxide Thin Film at Different Sn Doping Concentrations
p.276

HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 1109Ultra-Thin Body and Buried Oxide (UTBB) SOI...

Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs on Suppression of Short-Channel Effects (SCEs): A Review

Article Preview

Abstract:

This paper reviews the different UTBB SOI MOSFET structures and their superiority in suppressing short-channel effects (SCEs). As the gate length (L_g), buried oxide thickness (T_BOX) and silicon thickness (T_si) are scaled down, the severity of SCEs becomes significant. The different UTBB SOI MOSFET device structures introduced to suppress these SCEs are discussed. The effectiveness of these structures in managing the associated SCEs such as drain-induced barrier lowering (DIBL), subthreshold swing (SS) and off-state leakage current (I_off) is also presented. Further evaluations are made on other competing CMOS technologies such as multigate MOSFETs (FinFETs, three-gates, four-gates) and junctionless transistor in controlling the SCEs.

You might also be interested in these eBooks

Nanoscience, Nanotechnology, and Nanoengineering: Fundamentals and Applications

Info:

Periodical:

Advanced Materials Research (Volume 1109)

Pages:

257-261

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.1109.257

Citation:

Cite this paper

Online since:

June 2015

Authors:

Noraini Othman*, Mohd Khairuddin Md Arshad, Syarifah Norfaezah Sabki, U. Hashim

Keywords:

Short-Channel Effects (SCEs), UTBB SOI MOSFETs

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

© 2015 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

* - Corresponding Author

[1] S. Cristoloveanu, Silicon on insulator technologies and devices: from present to future, Solid. State. Electron., 45 (2001) 1403–1411.

DOI: 10.1016/s0038-1101(00)00271-9

[2] G. G. Shahidi, SO1 Technology for the GHz Era, IBM J. Res. Dev., 46 (2001) 11–14.

[3] J.-P. Colinge, Recent Advances and Trends in SOI CMOS Technology, Proc. Eur. Solid-State Device Res. Conf., 2 (1996).

[4] N. Kistler and J. Woo, Scaling Behaviour of Sub-micron MOSFETs on Fully-Depleted SOI, Solid State Electron., 39 (1996) 445–454.

DOI: 10.1016/0038-1101(95)00168-9

[5] T. Numata and S.-I. Takagi, Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs, IEEE Trans. Electron Devices, 51 (2004) 2161–2167. 2004.

DOI: 10.1109/ted.2004.839760

[6] C. Fenouillet-Beranger et. al, FDSOI devices with thin BOX and ground plane integration for 32nm node and below, Solid. State. Electron., 53 (2009) 730–734.

DOI: 10.1016/j.sse.2009.02.009

[7] A. Chaudhry and M. J. Kumar, Controlling Short-channel Effects in Deep Submicron SOI MOSFETs for Improved Reliability : A Review, IEEE Trans Device Mater. Reliab., 4 (2004) 99–109.

DOI: 10.1109/tdmr.2004.824359

[8] T. Tsuchiya et. al, Three Mechanisms Determining Short-Channel Effects in Fully-Depleted SOI MOSFET's, IEEE, 45 (1998) 1116–1121.

DOI: 10.1109/16.669554

[9] R.Yan et. al, Back-gate Mirror Doping for Fully Depleted Planar SOI Transistors with Thin Buried Oxide, VLSI Technology, System and Applications, (2010) 76–77.

DOI: 10.1109/vtsa.2010.5488939

[10] M. Saremi et. al, Process Variation Study of Ground Plane SOI MOSFET, 2nd Asia Symposium on Quality Electronic Design, 6(2010) 66–69.

DOI: 10.1109/asqed.2010.5548155

[11] C. Fenouillet-Beranger et. al, Impact of a 10nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32nm node and below, Solid. State. Electron., 54 (2010) 849–854.

DOI: 10.1016/j.sse.2010.04.009

[12] H. P. Wong et. al, Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gated Ultra-Thin SO1 MOSFET's at the 25 nm Chiannel Length Generation, IEDM Technical Digest, (1998) 407–410.

DOI: 10.1109/iedm.1998.746385

[13] L. Grenouille et. al, UTBB FDSOI transistors with dual STI for a multi-V t strategy at 20nm node and below, IEDM, (2012) 64–67.

[14] C. Sampedro, F. Gámiz, and A. Godoy, On the extension of ET-FDSOI roadmap for 22nm node and beyond, Solid. State. Electron., 90 (2013) 23–27.

DOI: 10.1016/j.sse.2013.02.057

[15] M. J. Kumar and M. Siva, The Ground Plane in Buried Oxide for Controlling Short-Channel Effects in Nanoscale SOI MOSFETs, IEEE Trans. Electron Devices, 55 (2008) 1554–1557.

DOI: 10.1109/ted.2008.922859

[16] H. Makiyama et. al, Novel Local Ground-Plane Silicon on Thin BOX ( SOTB ) for Improving Short-Channel-Effect Immunity, Euro SOI, 2 (2012) 27–28.

[17] R. Yan et. al, LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide, IEEE Transactions on Electron Devices, 57 (2010) 1319–1326.

DOI: 10.1109/ted.2010.2046097

[18] K. Cheng et. al, Fully Depleted Extremely Thin SOI Technology Fabricated by a Novel Integration Scheme Featuring Implant-Free, Zero-Silicon-Loss, and Faceted Raised Source/Drain, 2009 Symposium on VLSI Technology Digest of Technical Papers, (2009) 212-213.

[19] T. Nicoletti et. al, Advantages of different source/drain engineering on scaled UTBOX FDSOI nMOSFETs at high temperature operation, Solid State Electron., 91 (2014) 53–58.

DOI: 10.1016/j.sse.2013.09.012

[20] T. Nicoletti et. al, The impact of gate length scaling on UTBOX FDSOI devices: The digital/analog performance of extension-less structures, 2012 13th Int. Conf. Ultim. Integr. Silicon, (2012) 121–124.

DOI: 10.1109/ulis.2012.6193372

[21] V. Trivedi, J. G. Fossum, and M. M. Chowdhury, Nanoscale FinFETs With Gate-Source/Drain Underlap, IEEE Trans. Electron Devices, 52 (2005) 56–62.

DOI: 10.1109/ted.2004.841333

[22] D. Ranka et. al, Performance Analysis of FD-SOI MOSFET with Different Gate Spacer Dielectric, Int. J. Comput. Appl., 18 (2011) 22–27.

DOI: 10.5120/2280-2952

[23] M. Ma et. al, Impact of High- κ Offset Spacer in 65-nm Node SOI Devices, IEEE Electron Device Lett., 28 (2007) 238–241.

DOI: 10.1109/led.2007.891282

[24] K. Oshima et. al, Advanced SOI MOSFETs with buried alumina and ground plane: self-heating and short-channel effects, Solid. State. Electron., 48 (2004) 907–917.

DOI: 10.1016/j.sse.2003.12.026

[25] N. Bresson et. al, Integration of buried insulators with high thermal conductivity in SOI MOSFETs: Thermal properties and short channel effects, Solid. State. Electron., 49 (2005) 1522–1528.

DOI: 10.1016/j.sse.2005.07.015

[26] M. J. H. Van Dal et. al, Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography, 2007 Symp. VLSI Technol. Dig. Tech. Pap., (2007).

DOI: 10.1109/vlsit.2007.4339747

[27] V. Subramanian et. al, Planar Bulk MOSFET S Versus FinFETs : An Analog / RF Perspective, IEEE Trans. Electron Devices, 53 (2006) 3071–3079.

DOI: 10.1109/ted.2006.885649

[28] N. Singh et. al, High-performance fully depleted silicon nanowire (diameter < 5 nm) gate-all-around CMOS devices, IEEE Electron Device Lett., 27 (2006) 383–386.

DOI: 10.1109/led.2006.873381

[29] S. Bangsaruntip et al, High Performance and Highly Uniform Gate-All-Around Silicon Nanowire MOSFETs with Wire Size Dependent Scaling Epi, IEDM, (2009) 297–300.

DOI: 10.1109/iedm.2009.5424364

[30] J.-P. Colinge et. al, Nanowire transistors without junctions., Nat. Nanotechnol., 5 (2010) 225–9.

[31] J. P. Colinge et. al, Junctionless Nanowire Transistor (JNT): Properties and design guidelines, Solid. State. Electron., 65–66 (2011) 33–37.

DOI: 10.1016/j.sse.2011.06.004

[32] C.-Y. Chen, J.-T. Lin, and M.-H. Chiang, Performance optimization for the sub-22nm fully depleted SOI nanowire transistors, Solid. State. Electron., 92 (2014) 57–62.

DOI: 10.1016/j.sse.2013.11.002

[33] R. Trevisoli et. al, Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors," IEEE Trans. Electron Devices, 61 (2014) 1575–1582.

DOI: 10.1109/ted.2014.2309334

[34] C.-H. Park et. al, Electrical characteristics of 20-nm junctionless Si nanowire transistors, Solid. State. Electron., 73 (2012) 7–10.

[35] O. Faynot et. al, Planar Fully Depleted SOI Technology : a powerful architecture for the 20nm node and beyond, IEEE Electron Devices Meet., (2010) 50–53.

[36] O. Weber et. al, High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding, IEEE Electron Devices Meet., (2008) 10–13.

DOI: 10.1109/iedm.2008.4796663

[37] L. Clavelier et. al, Engineered Substrates for Future More Moore and More Than Moore Integrated Devices, IEEE Electron Devices Meet., (2010) 42–45.

DOI: 10.1109/iedm.2010.5703285