This paper introduces a leakage reduction technique using dual threshold CMOS in CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The leakage current source of the CPAL circuits is analyzed under nanometer CMOS processes. A 32 X 32 CPAL register file is demonstrated using the proposed dual threshold technique. In the proposed register file, the logic gates on critical path use low threshold transistors, while the other logic gates use dual threshold technique to reduce their leakage dissipations. All circuits are verified using HSPICE in different processes, threshold voltages, and operation frequencies, and BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses are obviously reduced both in active mode and idle mode.