Etching Effects of Nanotechnology Fabrication on CMOS Transistor Gate Wafer Manufacturing Process Integration

Abstract:

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As wafer nanotechnology gate is scaling down, the fabrication technology of gate spacer for transistor becomes more critical in manufacturing processes. Because wafer fabrication technologies, sidewall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present study is to overcome the fabrication processes limitations and proposed modified feasible etching processes integration on the formation processing for complementary metal oxide semiconductor nanofabrication process of gate spacer technology and electrical characteristics.

Info:

Periodical:

Advanced Materials Research (Volumes 154-155)

Edited by:

Zhengyi Jiang, Xianghua Liu and Jinglong Bu

Pages:

938-941

DOI:

10.4028/www.scientific.net/AMR.154-155.938

Citation:

C. J. Weng "Etching Effects of Nanotechnology Fabrication on CMOS Transistor Gate Wafer Manufacturing Process Integration", Advanced Materials Research, Vols. 154-155, pp. 938-941, 2011

Online since:

October 2010

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$35.00

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