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Sequential Circuit Equivalence Checking Method Based on Minimizing Automation
Abstract:
A parallel checking method is proposed in the paper, in order to improve the speed of sequential circuit checking. The graph form of sequential circuits is isomorphic to finite state machine; a parallel sequential circuit equivalence checking method is designed using parallel minimization method of finite state machine. At last, the effectiveness and feasibility of the method is proved with an instance.
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251-254
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Online since:
February 2011
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© 2011 Trans Tech Publications Ltd. All Rights Reserved
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