Sequential Circuit Equivalence Checking Method Based on Minimizing Automation
A parallel checking method is proposed in the paper, in order to improve the speed of sequential circuit checking. The graph form of sequential circuits is isomorphic to finite state machine; a parallel sequential circuit equivalence checking method is designed using parallel minimization method of finite state machine. At last, the effectiveness and feasibility of the method is proved with an instance.
Helen Zhang, Gang Shen and David Jin
Y. W. Gu et al., "Sequential Circuit Equivalence Checking Method Based on Minimizing Automation", Advanced Materials Research, Vols. 204-210, pp. 251-254, 2011