The Median Filtering Algorithm’s Fast Implementation in FPGA

Abstract:

Article Preview

Based on FPGA’S Balance and exchange principle of area and speed, Using the FPGA internal rich logic resources and powerful hardware characteristics , the traditional median filtering algorithm is reduced to 2 clock cycle , Greatly improving the image processing speed . And by using threshold, in a certain extent, reducing the image fuzzy phenomena brought by the median filter . The results of test show that the system runs stability, the time of achieving the median filtering algorithm are narrowed to the shortest clock cycle.

Info:

Periodical:

Advanced Materials Research (Volumes 230-232)

Edited by:

Ran Chen and Wenli Yao

Pages:

1054-1057

DOI:

10.4028/www.scientific.net/AMR.230-232.1054

Citation:

D. D. Zhang et al., "The Median Filtering Algorithm’s Fast Implementation in FPGA", Advanced Materials Research, Vols. 230-232, pp. 1054-1057, 2011

Online since:

May 2011

Export:

Price:

$35.00

In order to see related information, you need to Login.

In order to see related information, you need to Login.