The Median Filtering Algorithm’s Fast Implementation in FPGA
Based on FPGA’S Balance and exchange principle of area and speed, Using the FPGA internal rich logic resources and powerful hardware characteristics , the traditional median filtering algorithm is reduced to 2 clock cycle , Greatly improving the image processing speed . And by using threshold, in a certain extent, reducing the image fuzzy phenomena brought by the median filter . The results of test show that the system runs stability, the time of achieving the median filtering algorithm are narrowed to the shortest clock cycle.
Ran Chen and Wenli Yao
D. D. Zhang et al., "The Median Filtering Algorithm’s Fast Implementation in FPGA", Advanced Materials Research, Vols. 230-232, pp. 1054-1057, 2011