The Median Filtering Algorithm’s Fast Implementation in FPGA

Dao De Zhang; Yu Rong Pan; Xin Yu Hu; Guang You Yang; Cheng Xu

doi:10.4028/www.scientific.net/AMR.230-232.1054

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 230-232The Median Filtering Algorithm’s Fast...

The Median Filtering Algorithm’s Fast Implementation in FPGA

Abstract:

Based on FPGA’S Balance and exchange principle of area and speed, Using the FPGA internal rich logic resources and powerful hardware characteristics , the traditional median filtering algorithm is reduced to 2 clock cycle , Greatly improving the image processing speed . And by using threshold, in a certain extent, reducing the image fuzzy phenomena brought by the median filter . The results of test show that the system runs stability, the time of achieving the median filtering algorithm are narrowed to the shortest clock cycle.

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Periodical:

Advanced Materials Research (Volumes 230-232)

Pages:

1054-1057

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.230-232.1054

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Online since:

May 2011

Authors:

Dao De Zhang, Yu Rong Pan, Xin Yu Hu, Guang You Yang, Cheng Xu

Keywords:

Field-Programmable Gate Array (FPGA), Image Processing, Median Filtering, Threshold

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