Research on Multi-Core Collaborative Computing for FWP Image Processing Algorithm by FPGA

Abstract:

On the basis of analysis of research on embedded soft hardware collaborative design method, image processing SOPC collaborative design principle is elaborated, relation between complicated algorithm time and soft hardware implementation and the implementation method to accelerate algorithm by multi-processor and multi-core is studied, thus the logical relationship between equipment IP core on the chip with Fast Simplex Link(FSL) bus and bus bridge, connecting conditions and application flow is organized. Finally, design SOPC, for which, multi-core and multi-processor collaborative work with the core of PowerPC 405 processor by taking flexible workpiece path (FWP) image as an example. The test manifests that the computation speed of SOPC designed in this passage is higher 10 times than that of common single-core SOPC in terms of image processing computing, effectively solving the problem of slow speed for computing image preprocessing by software in the embedded system.

• Periodical: Advanced Materials Research (Volumes 230-232)
• Pages: 1340-1344
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.230-232.1340
• Online since: May 2011
• Authors: Yao Hua Deng, Gui Xiong Liu, Wei Han, Zi Wei Fang, Li Ming Wu, Qing Fu Liao
• Keywords: Collaborative Computing, FSL Bus, FWP Image Processing, Multi-Processor Core, SOPC

References

[1] Hiroaki Takada, Shinya Honda.: Hardware/Software Co-Configuration for Multiprocessor SoPC. IEEE Workshop on software Technologies for Future Embedded System(2003)85-86.

DOI: 10.1109/wstfes.2003.1201350

[2] Yuanrui Zhang, Mahmut Kandemir.: A Hardware-Software Codesign Strategy for Loop Inte.

[3] nsive Applications. In: 7th Symposium on Application Specific Processors. (2009)107-113.

[4] Liming Wu, Junxiu Liu.: Single Chip Fuzzy Control System Based on Mixed-Signal FPGA. In: International Conference on Intelligent Human-Machine Systems and Cybernetics. (2009)397-400.

DOI: 10.1109/ihmsc.2009.107

[5] Liming Wu, Junxiu Liu.: The Design of Co-processor for the Image Processing Single Chip System. In: International Conference on Computer Sciences and Convergence Information Technology. (2009)943-946.

DOI: 10.1109/iccit.2009.26

[6] Fernando P.R., Katkoori S., Keymeulen D.: Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine. IEEE Transactions on Evolutionary Computation, 14(1)2010, 133-149.

DOI: 10.1109/tevc.2009.2025032