Design of a Random Test Platform for DSP Serials Used in Embedded Systems

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Embedded systems with digital signal processor (DSP) become more and more popular for the increasing requirement of supercomputing these days. Efficient development of DSP serials used in embedded systems shortens the embedded system R&D cycle. Functional verification is one of the most complex and expensive tasks during DSP serials design process. A random test platform which is urged for DSP serials verification is proposed in this paper. The platform can automatically generate the random test program. The platform also realized the recording and checking of simulation results, which make the verification more effective. In order to improve the efficiency of DSP verification, a testing experience library has been generated through the testing procedure. This platform can be transplanted for different DSP models easily by updating few modules. According to the verification results, this platform has satisfactory coverage of DSP models.

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98-103

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June 2011

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© 2011 Trans Tech Publications Ltd. All Rights Reserved

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[1] Aharon, etc. Test Program Generation for Functional Verification of PowerPC Processors in IBM. Proceedings of the $2nd ACM/IEEE Design Automation Conference, June 1995. Page: 279-285.

DOI: 10.1109/dac.1995.249960

Google Scholar

[2] E. Bin, etc. Using a constraint satisfaction formulation and solution techniques for random test program generation. IBM System Journal Vol. 41, No. 3, 2002. Page: 386-402.

DOI: 10.1147/sj.413.0386

Google Scholar

[3] F. Corno, etc. Efficient Machine-Code Test-Program Induction. CEC2002: Congress on Evolutionary Computation, Honolulu, Hawaii (USA). Page: 1486-1491.

Google Scholar

[4] Wu, LM. Wang, KC. Chiu, CY. A BNF-based automatic test program generator for compatible microprocessor verification. ACM Transactions on Design Automation of Electronic Systems, 9(1): 105-132 JAN 2004. Page: 105-132.

DOI: 10.1145/966137.966142

Google Scholar

[5] Yingbiao Yao, etc. Pseudo-Random Program Generator. International Symposium on Integrated Circuits, 2007. Page: 441 - 444.

Google Scholar

[6] F. Corno, etc. Evolutionary test program induction for microprocessor design verification. Proceedings of the 11th Asian Test Symposium, 2002. Page: 368 - 373.

DOI: 10.1109/ats.2002.1181739

Google Scholar