Effect of Substrates on the Characteristics of Silicon Carbide Deposited from Methyltrichlorosilane

Abstract:

SiC is fabricated by chemical vapor deposition (CVD) on graphite and Si₃N₄ ceramic respectively. The morphology, composition, grain size and electrical conductivity of SiC deposited on graphite (CVD-SiC_(C)) and on Si₃N₄ ceramic (CVD-SiC_(N)) are investigated and compared. The morphology of CVD-SiC_(C) and CVD-SiC_(N) is much different with each other. The grain size of CVD-SiC_(C) is bigger than that of CVD-SiC_(N). It is nearly stoichiometric in CVD-SiC_(C), while carbon-rich in CVD-SiC_(N), so the electrical conductivity and dielectric loss of CVD-SiC_(N) are much higher than that of CVD-SiC_(C). As the annealing temperature increases, the grain size and electrical conductivity of CVD-SiC_(C) and CVD-SiC_(N) both increase.

• Periodical: Advanced Materials Research (Volumes 295-297)
• Pages: 1422-1427
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.295-297.1422
• Online since: July 2011
• Authors: Cui Ying Lu, Xiao Wei Yin, Xiang Ming Li
• Keywords: Chemical Vapor Deposition (CVD), Electrical Conductivity, Grain Size, Silicon Carbide (SiC)

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