High-Speed LMS Algorithm’s Design and Implementation Based on FPGA
This Paper Proposes a Kind of High-Speed Hardware Implementation Method by the Adaptive Equalizer (LMS Equalizer) Based on MSE Criteria. this Design First Makes Full Use of FPGA Internal Hardware on Time-Multiplier (DSP48Es), and Uses the High Throughput of the Streaming Design. then Reoccupy Matlab Software Simulation and Fixed Point Design, Finally Realized ML506 Development Board in Hardware Association Simulation. Experimental Proof, both the Simulation Results Are Consistent, and it Shows that the Proposed Algorithm Is Feasibility and Efficiency, and Has a High Application Value.
Riza Esa and Yanwen Wu
J. J. Liang et al., "High-Speed LMS Algorithm’s Design and Implementation Based on FPGA", Advanced Materials Research, Vols. 301-303, pp. 1157-1161, 2011