Design of a DSP System Based on FPGA

Ju Fang Hu; Chun Ru Xiong; Hao Hu; Run Yang Zhong

doi:10.4028/www.scientific.net/AMR.317-319.1559

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 317-319Design of a DSP System Based on FPGA

Design of a DSP System Based on FPGA

Abstract:

This paper proposes an innovative methodology to design a DSP (Digital Signal Processing) system using FPGA (Field-programmable Gate Array). There are several main components in this system, including A/D sampling unit, FFT processing unit and control unit. A/D sampling and FFT processing units utilize the Nios processor in FPGA as controller. Control unit uses EP1C20 FPGA chip from ALTERA as FFT processing unit so as to manage the FIFO operations. This unit can handle 128 FFT operations. This system design approach is tested on Matlab. The results indicate that the calculation speed is much faster than common DSP manner.

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Periodical:

Advanced Materials Research (Volumes 317-319)

Pages:

1559-1562

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.317-319.1559

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Online since:

August 2011

Authors:

Ju Fang Hu, Chun Ru Xiong, Hao Hu, Run Yang Zhong

Keywords:

Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), Pipelining, Radix-4

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References

[1] Baumgartner, D., et al., Benchmarks of Low-Level Vision Algorithms for DSP, FPGA, and Mobile PC Processors. Embedded Computer Vision, 2009: pp.101-120.

DOI: 10.1007/978-1-84800-304-0_5

Google Scholar

[2] Juang, J.C., et al., Design and implementation of an adaptive code discriminator in a DSP/FPGA-based Galileo receiver. GPS solutions, 2010. 14(3): pp.255-266.

DOI: 10.1007/s10291-009-0141-4

Google Scholar

[3] Li, H.R., et al., The Application of FPGA and DSP Techniques in Intelligent Wattmeter. Advanced Materials Research, 2011. 201: pp.2096-2100.

DOI: 10.4028/www.scientific.net/amr.201-203.2096

Google Scholar

[4] Jevtic, R., C. Carreras, and G. Caffarena, Fast and accurate power estimation of FPGA DSP components based on high-level switching activity models. International Journal of Electronics, 2008. 95(7): pp.653-668.

DOI: 10.1080/00207210801924024

Google Scholar

[5] Kwan, A.K.C., et al., Wireless Communications Transmitter Performance Enhancement Using Advanced Signal Processing Algorithms Running in a Hybrid DSP/FPGA Platform. Journal of Signal Processing Systems, 2009. 56(2): pp.187-198.

DOI: 10.1007/s11265-008-0225-3

Google Scholar

[6] Suzuki, D. and T. Matsumoto, How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation. IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, 2011. 94(1): pp.211-222.

DOI: 10.1587/transfun.e94.a.211

Google Scholar

[7] Shanthala, S. and S. Kulkarni, High Speed and Low Power FPGA Implementation of FIR Filter for DSP Applications. European Journal of Scientific Research, 2009. 31(1): pp.19-28.

Google Scholar