Platform Flash XCFP PROMs Updating Using JTAG Boundary-Scan

Abstract:

This paper demonstrates a method to update design revisions in the Platform Flash XCFP PROMs for configuration of Xilinx® FPGAs. The Platform Flash XCFP PROMs contain boundary-scan(JTAG) facilities that are compatible with IEEE Std 1149.1. Combining the FPGA configuration data (FPGA bitstream) into a PROM from GPIO ports of an embedded microcontroller through JTAG TAP interface of the PROM. The JTAG download method based on the GPIO ports of an embedded microcontroller can be implemented to erase, program, and verify the Platform Flash XCFP PROMs using IEEE Std 1149.1^[1]

• Periodical: Advanced Materials Research (Volumes 433-440)
• Pages: 4423-4427
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.433-440.4423
• Online since: January 2012
• Authors: Zhi Xian Zhang, Yuan Yao
• Keywords: FPGA Bitstreams, JTAG, TAP Controller

References

[1] IEEE Std 1149. 1-2001. IEEE Standard Test Access Port and Boundary-Scan Architecture [S]. (2001).

DOI: 10.1109/ieeestd.1995.122623

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[5] Xilinx XAPP972 (v1. 2). Updating a Platform Flash PROM Design Revision In-System Using SVF [Z]. (2009).