A Digital Regulator for FPGA Implementation

Abstract:

A digital regulator architecture implemented in FPGA is described which is used in the accelerator power supply. To save the delay time, the device is based on combinational circuit and special data format. The multiplier uses the partial products generated by modified Booth algorithm, Carry look-ahead adder and Wallace tree. The regulator is written in Verilog, and is synthesized into FPGA. The synthesis results shows that the proposed regulator can run 200MHZ clock rate in FPGA EP3C25F256 and the whole feedback time is as short as 3 clock periods.

• Periodical: Advanced Materials Research (Volumes 433-440)
• Pages: 4547-4554
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.433-440.4547
• Online since: January 2012
• Authors: Xiang Ping Qian, Wei Ming Qiao, Zhong Zu Zhou, Xi Meng Chen, Lan Jing
• Keywords: Booth Algorithm, Carry Look-Ahead Adder, Digital Regulator, Wallace Tree

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