A Hardware/Software Co-Design Flow for Dynamic Partial Reconfiguration

Abstract:

The strict requirements on both performance and flexibility lead us to apply Dynamic Partial Reconfiguration (DPR) technology in embedded systems. However, existing DPR design flows are still immature, since previous works mainly focus on hardware designs while ignore software designs for DPR. To remedy this weakness, this paper proposes a hardware/software (HW/SW) co-design flow for DPR. The co-design flow aims at accelerating the process of DPR designs, and it merges software and hardware design flows to make them operate in parallel. Besides, in order to validate the effectiveness of our co-design flow, we implement a partial self-reconfigurable prototype system on Xilinx Virtex-5 platform and perform a set of experiments. Experimental results present that the reconfiguration overhead for partial reconfiguration is only 4.66% against global reconfiguration in our prototype. It’s also presented that our prototype can achieve a 23.6 × speedup over software algorithm solutions.

• Periodical: Advanced Materials Research (Volumes 433-440)
• Pages: 5172-5177
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.433-440.5172
• Online since: January 2012
• Authors: Xiao Jing Feng, Xi Li, Wang Chao, Xue Hai Zhou, Jun Neng Zhang
• Keywords: Dynamic Partial Reconfiguration, Early Access Partial Reconfiguration, Hardware/Software Co-Design, Self Reconfiguration

References

[1] Azarian, A. and M. Ahmadi. Reconfigurable computing architecture survey and introduction. in Computer Science and Information Technology, 2009. ICCSIT 2009. 2nd IEEE International Conference on. (2009).

DOI: 10.1109/iccsit.2009.5234721

[2] Blodget, B., et al., A Self-reconfiguring Platform, in Field-Programmable Logic and Applications2003, Springer Berlin / Heidelberg. pp.565-574.

[3] Two Flows for Partial Reconfiguration: Module Based or Difference Based, 2004, Xilinx Inc.

[4] Early Access Partial Reconfiguration User Guide (For ISE 8. 1. 01i), 2006, Xilinx Inc.

[5] Partial Reconfiguration User Guide (For ISE 12. 3 release), 2010, Xilinx Inc.

[6] Nezami, K.G., P.W. Stephens, and S.D. Walker. Handel-C Implementation of Early-Access Partial-Reconfiguration for Software Defined Radio. in Wireless Communications and Networking Conference, 2008. WCNC 2008. IEEE. (2008).

DOI: 10.1109/wcnc.2008.199

[7] Claus, C., et al. A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. in Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International. (2007).

DOI: 10.1109/ipdps.2007.370362

[8] Yin, D., et al., Customizing virtual networks with partial FPGA reconfiguration, in Proceedings of the second ACM SIGCOMM workshop on Virtualized infrastructure systems and architectures2010, ACM: New Delhi, India. pp.57-64.

DOI: 10.1145/1851399.1851410

[9] Schallenberg, A., et al. SPP1148 booth: Seamless design flow for reconfigurable systems. in Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on. (2008).

DOI: 10.1109/fpl.2008.4629959

[10] Schallenberg, A., et al., OSSS+R: a framework for application level modelling and synthesis of reconfigurable systems, in Proceedings of the Conference on Design, Automation and Test in Europe2009, European Design and Automation Association: Nice, France. pp.970-975.

DOI: 10.1109/date.2009.5090805

[11] Weber, E., F. Dittmann, and N. Montealegre. Part-E - A Tool for Reconfigurable System Design. in Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on. (2008).

DOI: 10.1109/reconfig.2008.64

[12] LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2. 11c), 2010, Xilinx Inc.