IP Core Based Hardware Implementation of Multi-Layer Perceptrons on FPGAs: A Parallel Approach

Abstract:

There’re many models derived from the famous bio-inspired artificial neural network (ANN). Among them, multi-layer perceptron (MLP) is widely used as a universal function approximator. With the development of EDA and recent research work, we are able to use rapid and convenient method to generate hardware implementation of MLP on FPGAs through pre-designed IP cores. In the mean time, we focus on achieving the inherent parallelism of neural networks. In this paper, we firstly propose the hardware architecture of modular IP cores. Then, a parallel MLP is devised as an example. At last, some conclusions are made.

• Periodical: Advanced Materials Research (Volumes 433-440)
• Pages: 5647-5653
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.433-440.5647
• Online since: January 2012
• Authors: Xiao Jun Li, Lin Li
• Keywords: Artificial Neural Network (ANN), Backpropagation Algorithm, Field-Programmable Gate Array (FPGA), Hardware Implementation, Ip Core

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