A DFT Strategy for an Industrial Communications SoC with JTAG

Abstract:

In this paper a system level DFT strategy with JTAG is presented to test an industrial communication and control SoC . A SoC generally integrates that microprocessor, memories, some function blocks, PLL, D/A, A/D, etc. Cores originating from different sources need different test strategies. The different test techniques are used in testing of core-based SoC system which combines scan chains, Memory-BIST and Boundary-Scan. A SoC test with JTAG architecture is implemented through a real life case (0.18µm, million gates chip). The test pin counts are reduced, test time for board test is shorter and high test coverage is achieved.

• Periodical: Advanced Materials Research (Volume 461)
• Pages: 513-516
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.461.513
• Online since: February 2012
• Authors: Yi Zhuo Liu, Ke Xin Yin, Gang Liu, Hui Ran Sun
• Keywords: BIST, Boundary-Scan, DFT, JTAG, Scan

References

[1] Kiran George, Chien-In Henry Chen, Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip, 2008 IEEE Instrumentation and Measurement Technology Conference (I2MTC 2008), vol. 4  , Victoria, BC, Canada (2008).

DOI: 10.1109/imtc.2008.4547281

[2] Xin-Xin Wang, Li-Ping Liang and Xing-Jun Wang, A New Solution to Implement Multi-Full-Scan-Chain Test with JTAG, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, pp.2155-2157 (2006).

DOI: 10.1109/icsict.2006.306667

[3] Hamid H. Butt, ASIC DFT TECHNIQUES & BENEFITS, ASIC Conference and Exhibit, 1993, Proceedings, sixth annual IEEE international pp.46-53 (1993).

DOI: 10.1109/asic.1993.410804

[4] IEEE Std 1149. 1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE, INC.

DOI: 10.1109/ieeestd.1995.122623