COE Based on Redundancy Material Defect

Abstract:

In the nanometer technology node, the contradiction between high investment and low yield has got more and more prominent, so it plays a very significant role in improving the yield to optimize layout. The COE, Critical area On Edge network, which is a kind of network based on the redundancy material defect with edges expressing critical areas, is constructed in this paper. Vertexes stand for nets of the layout, and edges do short circuit areas existing in nets. By studying the applications of COE in DFM, it is indicated that the COE provides a new way to the research of nanometer node in DFM.

• Periodical: Advanced Materials Research (Volumes 472-475)
• Pages: 1792-1795
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.472-475.1792
• Online since: February 2012
• Authors: Jun Ping Wang, Pan Ning, Ruo Yu Pang, Jian Ping Fang
• Keywords: Critical Area, Critical Area on Edge Network., Layout Optimization, Redundancy Material Defect

References

[1] G. Zhang, P. Ma, X. Zhang, and Y. Hao, "Development of Critical Area Research Method for Integrated Circuits and Its Challenges," Microelectronics Journal, vol. 39, pp.704-709, 2009.(in Chinese)

[2] J. Wang and Y. Hao, "Short critical area computational method using mathematical morphology," in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) Xi'an, China, 2005, pp.796-803.

DOI: 10.1007/11596981_116

[3] T. S. Barnett, J. Bickford and A. J. Weger, "Product yield prediction system and critical area database," in ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings Stresa, Italy, 2007, pp.351-355.

DOI: 10.1109/asmc.2007.375062

[4] D. N. Maynard and J. D. Hibbeler, "Measurement and reduction of critical area using voronoi diagrams," in ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings Munich, Germany, 2005, pp.243-249.

DOI: 10.1109/asmc.2005.1438803

[5] S. Jansen, G. Florence, A. Perry, and S. Fox, "Utilizing design layout information to improve efficiency of SEM defect review sampling," in ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings Cambridge, MA, United states, 2008, pp.69-71.

DOI: 10.1109/asmc.2008.4529011

[6] S. Sinha, Q. Su, L. Wen, F. Lee, C. Chiang, Y. K. Cheng, J. L. Lin, and Y. C. Harn, "A new flexible algorithm for random yield improvement," in IEEE Transactions on Semiconductor Manufacturing 445 Hoes Lane / P.O. Box 1331, Piscataway, NJ 08855-1331, United States, 2008, pp.14-20.

DOI: 10.1109/tsm.2007.913187

[7] J. Wang and Y. Hao, "Yield modeling of arbitrary defect outline," in ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings Shanghai, China, 2007, pp.1183-1185.

DOI: 10.1109/icsict.2006.306070

[8] J. Wang, Z. Junming and H. Yue, "IC image segmentation using eigenvalue clustering," in 2007 IEEE International Workshop on Anti-counterfeiting, Security, Identification, ASID Xizmen, China, 2007, pp.184-187.

DOI: 10.1109/iwasid.2007.373723

[9] Q. Wang, J. Wang and C. Ren, "Critical Area Minimization Using the LP Method," Electronic Science and Technology. vol. 21, pp.1-4, 2008 (in Chinese) .

[10] J. Wang, Y. Hao, J. Zang, G. Ren, and H. Ni, "WCA with size and space distribution of real defects for 65-90nm processes," in 2nd International Conference on Anti-counterfeiting, Security and Identification, ASID 2008 Guiyang, China, 2008, pp.313-315.

DOI: 10.1109/iwasid.2008.4688426

[11] J. Wang, Y. Hao, H. Liu, and M. E. Jing, "Yield modeling based on circular defect size and a real defect rectangular degree," in International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT Beijing, China, 2004, pp.1104-1107.

DOI: 10.1109/icsict.2004.1436706