New Fault Isolation Method during Functional Test in Manufacturing

Abstract:

Stop Clock Design-for-Testability (DFT) and Scan Dump DFT are integrated and implemented to trap the digital logic inside combinational and sequential logics for fault isolation (FI) purpose. Both DFTs enable functional test result to be dumped out structurally during functional test at manufacturing. Validation is performed on RTL simulation using test pattern and it is shown that the real silicon data matched the simulation results. Hence a new FI method has been established on the fly, capable in manufacturing.

• Periodical: Advanced Materials Research (Volumes 479-481)
• Pages: 2572-2576
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.479-481.2572
• Online since: February 2012
• Authors: Li Ni Lee, Yee Fei Phuah
• Keywords: Design for Testability (DFT), Failure Analysis, Fault Isolation, Scan Dump, Stop Clock

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