VHDL- Based FPGA/CPLD Design Optimization Research

Xue Min Pang; Dao Jie Yu; Yu Hua Guo; Chang Lin Zhou

doi:10.4028/www.scientific.net/AMR.490-495.860

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 490-495VHDL- Based FPGA/CPLD Design Optimization Research

VHDL- Based FPGA/CPLD Design Optimization Research

Abstract:

The optimization of speed and area are the key points which must be put into consideration in FPGA/CPLD optimization design. In this paper, factors which affect the complexity of circuit structure are analyzed. The relationship which is difficult to balance between speed-optimization and area-optimization is also studied. Methods for speed-optimization and area-optimization are given respectively, and some examples in application are provided.

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Periodical:

Advanced Materials Research (Volumes 490-495)

Pages:

860-864

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.490-495.860

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Online since:

March 2012

Authors:

Xue Min Pang, Dao Jie Yu, Yu Hua Guo, Chang Lin Zhou

Keywords:

Key Path, Ping-Pong Operation, Pipeline Technology, Resource Sharing

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