An Improved Architecture for Multi-Core Prefetching

Juan Fang; Hong Bo Zhang

doi:10.4028/www.scientific.net/AMR.505.253

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 505An Improved Architecture for Multi-Core...

An Improved Architecture for Multi-Core Prefetching

Abstract:

The “Memory Wall” problem has become a bottleneck for the performance of processor, and on-chip multiprocessor(CMP) aggravates the memory access latency. So many hardware prefetching techniques have been brought to solve this challenge, i.e. Future Execution. This paper introduces runahead execution(another hardware prefetching technique firstly used on single-core processor) and Future Execution, then it brings up some improvement for Future Execution and gives the result and analysis of data tested by SPEC2000 benchmark.

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Periodical:

Advanced Materials Research (Volume 505)

Pages:

253-256

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.505.253

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Online since:

April 2012

Authors:

Juan Fang, Hong Bo Zhang

Keywords:

Architecture Register, CMP, IPC, Memory Access Latency

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