A High Resolution Vernier Ring Oscillator with Ultra-Low Temperature Drift

Abstract:

Nowadays, the precise measurement of the time interval between two events with very fine timing resolution is common challenge in the test and measurement instrumentation. This paper present a new high resolution vernier ring oscillator(VRO), which can measures the clock jitter as the operation temperature rises.The goal of this work focuses on the design of a TDC of temperature stable oscillator and we propose an ultra-low temperature drift of a differential delay cell oscillator based on a proportional to absolute temperature(PTAT) compensation methodology. It is very desirable to have a single integrated circuit producing a stable high resolution timing circuit over a wide temperature range developed in a standard CMOS process. By the simple concept of vernier delay line and two ring oscillators, the proposed can achieve a fine time resolution with wide working temperature. For each channel of ring oscillator, the relative delay time is fine tuned by an external VBIAS input. From 25°Cto 45°C, the maximum error percent of delay time without compensation circuits is more than 2.9%, but it with compensation circuits is less than 0.3%. The different operating temperature will affect entire circuit and the delay time of ring oscillator. A compensation circuit to reduce the variety of ring oscillator is also added. The new architecture of high resolution TDC with temperature compensated circuit is proven to be applicable in high precision clock applications which is analyzed and implemented in a CMOS 0.18μm 1P6M process.

• Periodical: Advanced Materials Research (Volumes 542-543)
• Pages: 795-799
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.542-543.795
• Online since: June 2012
• Authors: Rui Hong Liu, Chih Hsiung Shen
• Keywords: PTAT, Vernier Delay Line, Vernier Ring Oscillator

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