A Novel Dual-Mode Low Pass Sigma-Delta Modulator Chip Design for WCDMA and Bluetooth Applications

Jhin Fang Huang; Wen Cheng Lai; Kun Jie Huang; Ron Yi Liu

doi:10.4028/www.scientific.net/AMR.660.113

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 660A Novel Dual-Mode Low Pass Sigma-Delta Modulator...

A Novel Dual-Mode Low Pass Sigma-Delta Modulator Chip Design for WCDMA and Bluetooth Applications

Abstract:

A dual-mode low pass sigma-delta (ΣΔ) modulator at clock rates of 160 and 100 MHz respectively with cascaded integrators is presented for WCDMA and Bluetooth applications. One of main features is that cascaded integrators with feedback as well as distributed input coupling (CIFB) topology erase a summation amplifier and save power consumption. Another feature is that only one set loop filter is designed by switching capacitors to achieve a dual-mode function and greatly saves chip area. A prototype is fabricated in TSMC 0.18-m CMOS process. At the supply voltage of 1.8 V, measured results have achieved the SNDR of 42/33 dB over 1/2 MHz, respectively for Bluetooth/WCDMA. The chip dissipates a low power of 10.5 mW. Including pads the chip area is only 0.61 (0.71× 0.86) mm².

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Periodical:

Advanced Materials Research (Volume 660)

Pages:

113-118

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.660.113

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Online since:

February 2013

Authors:

Jhin Fang Huang, Wen Cheng Lai, Kun Jie Huang, Ron Yi Liu

Keywords:

Bluetooth, Dual-Mode Low Pas, Sigma-Delta (ΣΔ) Modulator, WCDMA

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