Low Power Implementation of AES Mix Columns/ Inverse Mix Column on FPGA

Abstract:

With the widespread use of battery operating systems, low power designs are highly needed to extend the battery lifetime. Encryption/ decryption circuits are one of the best candidates for low power implementation, as they are needed to maintain the privacy and security of user data. In this work, we present a low power FPGA-based implementation for AES Mix Columns (MC) /Inverse Mix Columns (IMC). The proposed design achieves low power by applying precomputation and resource sharing techniques to the MC and IMC transformation. We compared this implementation with previous work and we found that this implementation provides an average of 28% less power than previous implementations.

• Periodical: Advanced Materials Research (Volume 677)
• Pages: 311-316
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.677.311
• Online since: March 2013
• Authors: Marwa Sleem, Yousra Alkabani, Ali Rashed, Attif Ibraheem
• Keywords: AES, Field-Programmable Gate Array (FPGA), Low Power Design, Security

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