Fitting Mixtures of Gaussians to Heavy-Tail Distributions to Analyze Fail-Bit Probability of Nano-Scaled Static Random Access Memory

Worawit Somha; Hiroyuki Yamauchi; Yan Zhang

doi:10.4028/www.scientific.net/AMR.677.317

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 677Fitting Mixtures of Gaussians to Heavy-Tail...

Fitting Mixtures of Gaussians to Heavy-Tail Distributions to Analyze Fail-Bit Probability of Nano-Scaled Static Random Access Memory

Abstract:

This paper proposes a fitting method to approximate a heavy-tailed Gamma distribution characterizing the random telegraph noises by simple Gaussian mixtures model (GMM). The concepts central to the proposed method are 1) adaptive segmentation of the long-heavy tailed distributions such that the log-likelihood of GMM in each partition is maximized and 2) copy and paste with an adequate weight into each partition. It is verified that the proposed method can reduce the error of the fail-bit predictions by 2-orders of magnitude while reducing the iterations for EM step convergence to 1/16 at the interest point of the fail probability of 10-12 which corresponds to the design point to realize a 99.9% yield of 1Gbit chips.

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Periodical:

Advanced Materials Research (Volume 677)

Pages:

317-325

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.677.317

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Online since:

March 2013

Authors:

Worawit Somha, Hiroyuki Yamauchi, Yan Zhang

Keywords:

EM Algorithm, Fail-Bit Analysis, Heavy-Tail Distribution, Mixtures of Gaussian, Random Telegraph Noise, Static Random Access Memory

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References

[1] H. Yamauchi, A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Vol. 18 (2010), Issue : 5, pp.763-774.

DOI: 10.1109/tvlsi.2009.2016205

Google Scholar

[2] H. Yamauchi, Embedded SRAM trend in nano-scale CMOS, Memory Technology, Design and Testing, MTDT 2007. IEEE International Workshop on (2007), pp.19-22.

DOI: 10.1109/mtdt.2007.4547608

Google Scholar

[3] H. Yamauchi, tutorials Variation tolerant SRAM circuit design, in IEEE ISSCC 2009 and IEEE A-SSCC 2008.

Google Scholar

[4] K. Takeuchi, et al, Comprehensive SRAM Design Methodology for RTN Reliability, , Digest of IEEE Symposium on VLSI Technology, (2011), pp.130-131.

Google Scholar

[5] Moon, T. K, The expectation-maximization algorithm, in Signal Processing Magazine, IEEE, Volume: 13 , Issue: 6, p.47 – 60 (1996).

DOI: 10.1109/79.543975

Google Scholar