Design and Verification of a "Soft" eFPGA Using New Method

Article Preview

Abstract:

A novel design methodology for soft eFPGA is proposed. In comparison with the previous soft core design approach, a structured-description strategy is applied and the process of logic synthesis is bypassed in the new design flow. Thus, the capability of processing the bidirectional routing architectures of the mainstream eFPGAs is obtained, while the conventional soft core design method could only handle the eFPGA with directional routing structure. Moreover, the experiment result shows eFPGA designed with this new method is 2 times denser than that designed with the conventional method. To verify this method, a proof-of-concept eFPGA prototype is designed and also presented.

You might also be interested in these eBooks

Info:

Periodical:

Pages:

301-306

Citation:

Online since:

June 2013

Keywords:

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2013 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] B.Neumann, T.vonSydow, H.Blume, et al, Design flow for embedded FPGAs based on a flexible architecture template. Proceedings of Design, Automation and Test in Europe, 2008,pp.56-61.

DOI: 10.1109/date.2008.4484660

Google Scholar

[2] J.Wu,V.Aken'Ova, S.Wilton, et al, SoC Implementation Issues for Synthesizable Embedded Programmable Logic Cores. Proceedings of the Custom Integrated Circuits Conference, 2003,pp.45-48.

DOI: 10.1109/cicc.2003.1249356

Google Scholar

[3] V.Aken'Ova, R.Saleh, A "soft++" eFPGA physical design approach with case studies in 180nm and 90nm. IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 2006,pp.103-108.

DOI: 10.1109/isvlsi.2006.1

Google Scholar

[4] S.Wilton, N.Kafafi, J.Wu, et al, Design considerations for soft embedded programmable logic cores. IEEE Journal of Solid-State Circuits, 2005, 40(02),pp.485-496.

DOI: 10.1109/jssc.2004.841038

Google Scholar

[5] N. Kafafi, K. Bozman, S. Wilton, Architecture and algorithms for synthesizable embedded programmable logic cores. ACM international symposium on FPGA,2003,pp.3-11.

DOI: 10.1145/611817.611820

Google Scholar

[6] I.Kuon, A. Egier, J. Rose. Design, Layout and Verification of an FPGA using Automated Tools. ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA, 2005,pp.215-226.

DOI: 10.1145/1046192.1046220

Google Scholar

[7] K. Padalia, R. Fung, M. Bourgeault, et al, Automatic transistor and physical design of FPGA tiles from an architectural specification. ACM international symposium on FPGA,2003,pp.164-172.

DOI: 10.1145/611817.611842

Google Scholar

[8] V. Betz, J. Rose, VPR: A new packing, placement and routing tool for FPGA research[C]. ACM international symposium on FPGA, 1997,pp.213-222.

DOI: 10.1007/3-540-63465-7_226

Google Scholar

[9] Information on http://university.altera.com/research/unv-quip.html.

Google Scholar

[10] V. Betz, J. Rose, A, Marquardt.Architecture and CAD for Deep-Submicron FPGAs.Kluwer Academic Publishers, 01(1999) 38-67.

DOI: 10.1007/978-1-4615-5145-4

Google Scholar